THE DESIGN OF A 10-BIT PIPELINE ANALOG-TO-DIGITAL CONVERTER
碩士 === 大同工學院 === 電機工程學系 === 85 === This thesis describes the design of a low-power, low-voltage, 10-bit, and 1 M sample/s pipeline analog-to-digital converter that operates at a 3.3-V supply with static power dissipation of 22.8 mW. The con...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37406053740207461896 |