VLSI Architecture Designs of Grey Model

• Main Authors: Wang, Si-hwa, 王世華
• Other Authors: Wu Chwan-chia
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/35563440049948740253

碩士 === 國立台灣工業技術學院 === 電機工程技術研究所 === 85 === The thesis propose a hardware architecture to eliminate the bottleneck of grey model construction and prediction. To solve the problem of applying grey model in some real-time systems, we present a grey predictor architecture with 12 bits fixed-point input and optional confine for the sampled data numbers and predictive time. Fixed-point input format will simplify hardware complexity, reduce predictive time and make it easy to match with analog-digitalconverter or micro-controller. Furthermore, this system includes the parallel processing and pipeline technique in grey model construction and predictor to provide better performance than the software system. In specification, this architecture eliminate unnecessary design to reduce system cost and increase the system processing performance. The predic- tive output error is small than 0.5% compared with GM(1,1) algorithm, and the predictive time is about 60 clock cycles (less than 1 msin 66MHz clock rate). If this architecture is implemented with VLSI process, it will greatly reduce the computational load of coprocessor or CPU to increase the ability for decision making. Especially, this system will increase the suitability of real-timegrey predictive control system.