| Summary: | 碩士 === 國立台灣工業技術學院 === 電子工程技術研究所 === 85 === The weighted median filter is usually used to remove spike
noises and impulsive noises of image signal but, at same time,
preserves the edge information. Hence, in this thesis, we design
a 16-input weighted median filter with the cell-based approach.
The main idea of the weighted median filter designed in the
thesis is based on Bitonic sorting network. In addition, a
special circuit is used to complete the weight processing
operations. The resulting system shows that a median can be
generated in l+m+17 clocks, where l is the word length and m(1<=
m<=16) is the median position. In addition, the circuit can be
used as a 16 l-bit serial data input sorting network. When using
as a sorting network, it only needs 12 clocks to generate the
sorted results. Furthermore, the circuit is also cascadable.
That is, many chips can be cascaded to form a larger fan-in
weighted median filter/sorting network.Finally, the chip is
realized with the COMPASS 0.6um standard cell library and TSMC
0.6um CMOS SPDM technology. The chip occupies 4193um*3733um and
dissipates 896 mW at clock rate of 55.56 MHz.
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