| Summary: | 碩士 === 國立臺灣大學 === 電機工程學系 === 85 === In this thesis, we propose a low hardware cost motion estimator
for ITU-T Recomm-comm-endation H.263 standard. The advanced
modes of H.263 and the half-pixel precision of motion estimation
are considered in this architecture. As the required throughput
of the motion estimator for H.263 is not very high, we adopted
linear array to implement the low hardware cost, high hardware
utilization architecture. The half-pixel precision requirement
of H.263, compared with H.261 standard, is included in this
architecture. The advanced modes of the standard: Advanced
Prediction mode and PB-frame mode are also included in the
proposed architecture. This architecture of H.263 performs the
motion estimation of the macroblock and 8’8 blocks concurrently
and this satisfies the requirement of the AP mode. The PB-frame
mode supplies the bit rate reduction scheme in the H.263. We
implement the motion estimation of the B-picture with the same
PE array architecture. The whole chip includes two main part:
IU, which performs the integer-pixel precision motion estimation
and HU, which produces the half-pixel precision block matching
of the candidate blocks. In the IU, normal FSBM, AP mode and PB-
frame mode are performed by the same PE array architecture and
the total hardware cost is reduced to minimum. On the other
hand, We propose the single PE architecture to perform the half-
pixel precision motion estimation. The modified interpolation
unit is also proposed to satisfy the PE architecture.
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