The design of pipelined A/D converter
碩士 === 國立臺灣大學 === 電機工程學系 === 85 === Pipelined ADC is one of the advance high speed high resolution ADCarchitectures. Compared to other architectures used in similiar applications , it consumes lower power. One of its drawbacks is the difficulty of desig...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/05662063408892724725 |
| Summary: | 碩士 === 國立臺灣大學 === 電機工程學系 === 85 === Pipelined ADC is one of the advance high speed high resolution
ADCarchitectures. Compared to other architectures used in
similiar applications , it consumes lower power. One of its
drawbacks is the difficulty of design due to its complexity of
circuits.In this dissertation, a 10-bit pipelined ADC has been
designed by theUMC 0.5um DPDM process. Simulation results show
that it can work properlyat 10MSPS with the maximum error of
0.4LSB. Its power consumption is about32mW. At the end of this
dissertation , some ADC testing methods are discussedwith a demo
of AD875 testing.
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