Optimization of parasitic capacitance for multilevel interconnection

碩士 === 國立清華大學 === 電機工程學系 === 85 ===

Bibliographic Details
Main Authors:	Yeh, Cheng-kuo, 葉正國
Other Authors:	Lien Cheng-Hsin
Format:	Others
Language:	zh-TW
Published:	1997
Online Access:	http://ndltd.ncl.edu.tw/handle/28922540059019908115

id	ndltd-TW-085NTHU0442071
record_format	oai_dc
spelling	ndltd-TW-085NTHU04420712015-10-13T18:05:32Z http://ndltd.ncl.edu.tw/handle/28922540059019908115 Optimization of parasitic capacitance for multilevel interconnection 多層內連線寄生電容的模擬最佳化 Yeh, Cheng-kuo 葉正國碩士國立清華大學電機工程學系 85 Lien Cheng-Hsin 連振炘 1997 學位論文 ; thesis 68 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立清華大學 === 電機工程學系 === 85 ===
author2	Lien Cheng-Hsin
author_facet	Lien Cheng-Hsin Yeh, Cheng-kuo 葉正國
author	Yeh, Cheng-kuo 葉正國
spellingShingle	Yeh, Cheng-kuo 葉正國 Optimization of parasitic capacitance for multilevel interconnection
author_sort	Yeh, Cheng-kuo
title	Optimization of parasitic capacitance for multilevel interconnection
title_short	Optimization of parasitic capacitance for multilevel interconnection
title_full	Optimization of parasitic capacitance for multilevel interconnection
title_fullStr	Optimization of parasitic capacitance for multilevel interconnection
title_full_unstemmed	Optimization of parasitic capacitance for multilevel interconnection
title_sort	optimization of parasitic capacitance for multilevel interconnection
publishDate	1997
url	http://ndltd.ncl.edu.tw/handle/28922540059019908115
work_keys_str_mv	AT yehchengkuo optimizationofparasiticcapacitanceformultilevelinterconnection AT yèzhèngguó optimizationofparasiticcapacitanceformultilevelinterconnection AT yehchengkuo duōcéngnèiliánxiànjìshēngdiànróngdemónǐzuìjiāhuà AT yèzhèngguó duōcéngnèiliánxiànjìshēngdiànróngdemónǐzuìjiāhuà
_version_	1718028352202211328

Optimization of parasitic capacitance for multilevel interconnection

Similar Items