| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 85 === In this thesis, we present the improved World-Wide-Web (WWW)
version of theEvaluation System for TEst Engineering
Methodologies (ESTEEM2),to aid decision making with regard to
which test methodology should be usedto develop a VLSI chip or
system. Many managers consider design for testability (DFT) to
be an "overhead" for development and production cost.Our system,
however, takes a full consideration on the relation between DFT
and various time models. We will show that DFT mayactually help
engineers to shorten the total time needed in product
developmen, which leads to lower man-power cost and shorter time
to market,and therefore results in more revenue through out the
product's life time.Production cost may also be reduced due to
lower testing cost. If managers consider only the area overhead
of DFT, they mayfind that design without testability actually
costs more,especially for VLSI chips and systems. Our system
uses time-related cost and revenue models. It helps managers
toevaluate different DFT methodologies to reduce overall cost
and/orincrease overall revenue. ESTEEM2 is developed with C,
mSQL, and Apache Web Server.The user access the system using web
browsers such as Netscape.We propose cost and revenue models for
default calculation, but user specified models are allowed.
There is a built-indemo circuit --- an IEEE 1149.5 MTM-Bus slave
module chip --- showingour proposed system parameters. Every
user can copy this demo circuit to his own folder and adjust the
parameters to meet needs.This is an on-going project, with more
realistic and complete costand revenue models and test
methodologies to be developed and included in the future.
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