Analysis of Increasing the Flexibility of LBs of Matrix-based FPGAs to Achieve Low Power Consumption

碩士 === 國立中山大學 === 電機工程研究所 === 85 === The large resistance and capacitance of the connection switches in Field Programmable Gate Arrays (FPGA) routing tracks consume a great portion of total power and cause large delays no matter what technology is used for the programmable connections. Hence,...

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Bibliographic Details
Main Authors:	Huang, Chia-Fu, 黃加富
Other Authors:	Wang, Chua-Chin
Format:	Others
Language:	zh-TW
Published:	1997
Online Access:	http://ndltd.ncl.edu.tw/handle/03352156139372311216

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spelling	ndltd-TW-085NSYS34420322015-10-13T18:05:28Z http://ndltd.ncl.edu.tw/handle/03352156139372311216 Analysis of Increasing the Flexibility of LBs of Matrix-based FPGAs to Achieve Low Power Consumption 增加矩陣式場效可程式化邏輯陣列區塊接腳選擇度以達成低功率之分析 Huang, Chia-Fu 黃加富碩士國立中山大學電機工程研究所 85 The large resistance and capacitance of the connection switches in Field Programmable Gate Arrays (FPGA) routing tracks consume a great portion of total power and cause large delays no matter what technology is used for the programmable connections. Hence, the reduction of the average number of the connection switches per net can lead to the power and delay reduction of the whole circuit. Consequently the performance of mapped circuits will be improved. We propose to double the pins of each input or output and arrange the two pins of each I/O symmetrically in the logic block (LB). An analytic general from solution of the reduction ratio of switch count is presented. Finally, thorough simulation results of certain benchmark circuits showing the impact on the power and delay are presented to verify the theoretical analysis. Wang, Chua-Chin 王朝欽 1997 學位論文 ; thesis 51 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立中山大學 === 電機工程研究所 === 85 === The large resistance and capacitance of the connection switches in Field Programmable Gate Arrays (FPGA) routing tracks consume a great portion of total power and cause large delays no matter what technology is used for the programmable connections. Hence, the reduction of the average number of the connection switches per net can lead to the power and delay reduction of the whole circuit. Consequently the performance of mapped circuits will be improved. We propose to double the pins of each input or output and arrange the two pins of each I/O symmetrically in the logic block (LB). An analytic general from solution of the reduction ratio of switch count is presented. Finally, thorough simulation results of certain benchmark circuits showing the impact on the power and delay are presented to verify the theoretical analysis.
author2	Wang, Chua-Chin
author_facet	Wang, Chua-Chin Huang, Chia-Fu 黃加富
author	Huang, Chia-Fu 黃加富
spellingShingle	Huang, Chia-Fu 黃加富 Analysis of Increasing the Flexibility of LBs of Matrix-based FPGAs to Achieve Low Power Consumption
author_sort	Huang, Chia-Fu
title	Analysis of Increasing the Flexibility of LBs of Matrix-based FPGAs to Achieve Low Power Consumption
title_short	Analysis of Increasing the Flexibility of LBs of Matrix-based FPGAs to Achieve Low Power Consumption
title_full	Analysis of Increasing the Flexibility of LBs of Matrix-based FPGAs to Achieve Low Power Consumption
title_fullStr	Analysis of Increasing the Flexibility of LBs of Matrix-based FPGAs to Achieve Low Power Consumption
title_full_unstemmed	Analysis of Increasing the Flexibility of LBs of Matrix-based FPGAs to Achieve Low Power Consumption
title_sort	analysis of increasing the flexibility of lbs of matrix-based fpgas to achieve low power consumption
publishDate	1997
url	http://ndltd.ncl.edu.tw/handle/03352156139372311216
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Analysis of Increasing the Flexibility of LBs of Matrix-based FPGAs to Achieve Low Power Consumption

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