Analysis of Increasing the Flexibility of LBs of Matrix-based FPGAs to Achieve Low Power Consumption
碩士 === 國立中山大學 === 電機工程研究所 === 85 === The large resistance and capacitance of the connection switches in Field Programmable Gate Arrays (FPGA) routing tracks consume a great portion of total power and cause large delays no matter what technology is used for the programmable connections. Hence,...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/03352156139372311216 |
| Summary: | 碩士 === 國立中山大學 === 電機工程研究所 === 85 ===
The large resistance and capacitance of the connection switches in Field Programmable Gate Arrays (FPGA) routing tracks consume a great portion of total power and cause large delays no matter what technology is used for the programmable connections. Hence, the reduction of the average number of the connection switches per net can lead to the power and delay reduction of the whole circuit. Consequently the performance of mapped circuits will be improved. We propose to double the pins of each input or output and arrange the two pins of each I/O symmetrically in the logic block (LB). An analytic general from solution of the reduction ratio of switch count is presented. Finally, thorough simulation results of certain benchmark circuits showing the impact on the power and delay are presented to verify the theoretical analysis.
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