Internal Connection Network for an Advanced Microprocessor
碩士 === 國立東華大學 === 資訊工程研究所 === 85 === In recent years, superscalar architecture becomes a popular approach forimplementing high-performance microprocessor. By using dynamic scheduling toexploit instruction level parallelism at run-time...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83058420621615066723 |
| Summary: | 碩士 === 國立東華大學 === 資訊工程研究所 === 85 === In recent years, superscalar architecture becomes a
popular approach forimplementing high-performance
microprocessor. By using dynamic scheduling toexploit
instruction level parallelism at run-time, the superscalar
processorcan reduce average number of cycles per instruction and
thus achieves better performance. The thesis presents the design
of the ALU reservation stationand result switching network for
an advanced microprocessor. The advanced microprocessor is a
64-bit superscalar X86 instruction compatible processorand its
expected to run at a speed of 150 MHz. We employ the
cluster-type reservation station as our ALU RS and multiplebuses
as our result switching network. The ALU RS is between the
dispatcher,operand preparation and the ALU units. It is
responsible for selecting theappropriate instructions to issue
to ALU functional units for execution. Theresult switching
network is responsible for carrying the results producedby the
functional units to the the reorder associative buffer and the
reservation station. These results are used to update the
operands of theinstructions that wait in the reservation station
and the reorder associativebuffer for their operands to become
available.
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