Complete Interconnect BIST Using IEEE 1149 Boundary Scan
碩士 === 國立中央大學 === 電機工程學系 === 85 === In this paper, we will present a BIST methodology for board and system levels interconnect based on IEEE 1149.1 and IEEE 1149.5 Boundary Scan standards. We target at systems with optional cards. We will p...
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95648108283267675920 |
| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 85 === In this paper, we will present a BIST methodology for board and
system levels interconnect based on IEEE 1149.1 and IEEE 1149.5
Boundary Scan standards. We target at systems with optional
cards. We will proposed an algorithm that is able to generate
suitable test pattern for dynamic option card environment.The
system test flow is composed of tests for scan paths, intra/
inter nets, and backplane net. To verify our algorithm, we will
present the hardware emulator to emulate the proposed test
methodology in IEEE 1149.5 and IEEE 1149.1 environments.
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