| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 85 ===
In motion pictures compression process, motion estimation is a widely used technique. Motion estimation is adopted to explot the temporal redundancy existed among successive frames in a motion picture sequence. By utilizing this temporal redundancy, the storage capacity and transmission bandwitdth can be reduced. Along with this motion estimation technique, requirement of huge frame memory bandwidth is introduced. The amount of bandwidth is beyond the current technique can afford. The set up of on chip memory can effectively deal with this problem. The size of on chip memory, organization of the on chip memory and its interface to PEs have to be carefully considered. These are discussed in this dissertation.
First the basis of motion estimation is described. Various search algorithms and published architectures for motion estimation are also discussed briefly. Then the reason why motion estimation process consumes huge bandwidth is explained. Property of data reuse is analyzed. Such property can be used to reduce the required frame memory bandwidth by the cost of on chip memory. Under different degrees of data reuse, the required on chip memory size differs. Analysis of on chip memory organization and its interface to PEs are applied to presented architectures. According to our analysis, a high efficiency architecture which meets the minimum memory bandwidth is proposed.
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