Parallel Solution of Matrix Inversion for Semiconductor Device Simultaion

• Main Authors: Shen, Jev-Jyh, 沈志哲
• Other Authors: Shuang-Fa Guo
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/68102441507379146986

碩士 === 國立交通大學 === 電子工程學系 === 85 === In this work, we implement equation parallelization and grid-point parallelization for semiconductor device simulation using the CONVEX SPP-1000 parallel computer in the PVM environment. In equation parallelization, we solve the three basic equations concurrently. The speedup of equation parallelization is about 1.52. Because of the asymmetric characteristics of coefficient matrix, a BiCGST algorithm has been employed to achieve better convergence. The convergence speed is decided by the choice of the preconditioning matrix. Three parallel preconditioners: truncated IC factorization, conventional polynomial, and Chebyshev polynomial have been compared in this work. The grid-point parallelization is based on the parallel preconditioner in BiCGST algorithm. The truncated IC factorization and conventional polynomial preconditioners have almost the same performance. The Chebyshev polynomial preconditioner can reduce the computation time by a factor of 1.24.Because the CPU time required in parallel algorithm is longer than that required in serial algorithm by a factor of about 5.61 using sequential computation, the speedup of grid-point parallelization is only 1.72 using 6 processes in the PVM environment.