Issues of the RISC Execution Core for a Superscalar CISC Microprocessor

• Main Authors: Sheu, Yuh-Ren, 許裕仁
• Other Authors: Chang-Jiu Chen
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/36939627583475659122

碩士 === 國立交通大學 === 資訊工程學系 === 85 === Originally, Intel x86 processor is a scalar CISC processor, i.e. it can finish one x86 instruction per cycle at the most. Due to the inhibitive cost and the limitation of semiconductor process technology and electrical property, we cannot lift up the clock speed of x86 processor unendingly to gain much more performance improvement. It seems straightforward that we can build a 2-way issue superscalar x86 processor just by adding another one integer pipeline to he original scalar x86 architecture. But the inherent characteristics of x86 instruction set constrain the overall improvement.One way to approach the superscalar x86 processor design is to start with a pure microcoded scalar implementation, without hardwired control and special techniques employed in the Intel x86 processor. The goal in this case would be to archive parallel execution of microinstructions in a superscalar pipeline. The advantages of this approach is that it converts complex x86 instructions into sequences of microinstructions that are much easier to deal with.Although we can design a superscalar CISC processor with RISC execution core to improve overall performance. In this design, the other advantage is that we can save a lot of money and time by using existed technique or implementation for RISC processor to build the RISC execution core [7]. But the thing is not so good, we need to adapt the existed RISC design to fit the CISC architecture. We will address theses issues and advise possible solutions.