| Summary: | 碩士 === 國立交通大學 === 資訊工程學系 === 85 === This thesis proposes a method to design the decoder
architecture, for decoding and translating X86 instructions to
RISC-like instructions. Thedecoder architecture augments X86
instruction level parallelism to the processor and produces more
micro operation outputs. This decoder contains a prefetcher, a
predecoder, a predecoded instruction buffer and instruction
converters with guarded-execution instructions. We adopt some
different strategy in the prefetcher to fetch instructions from
instruction cache. When the instruction path contains a
conditional branch instruction with forward and short distance
target, the prefetcher will be do less job than an ordinary
prefetcher. This strategy will accommodate converters with
guarded-execution instructions. We use a behavior simulation
with real X86 instruction codes. The evaluation results show
that the proposed translating architecture can translate more
instructions every cycle.
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