Design and Evaluation of A X86 CISC/RISC Translation Architecture
碩士 === 國立交通大學 === 資訊工程學系 === 85 === This thesis proposes a method to design the decoder architecture, for decoding and translating X86 instructions to RISC-like instructions. Thedecoder architecture augments X86 instruction level parallelis...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99925280171219991545 |