The Study of Global Production Lot Sizing in Wafer Fabrication Measured by Cycle time

• Main Authors: Chang, Yi-Cheng, 張益誠
• Other Authors: Lee Ching-En
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/69198597320089758590

碩士 === 國立交通大學 === 工業工程與管理學系 === 85 === To gain the competitive advantage, cycle time reduction is one of the most critical issues in wafer fabrication (especiallyin wafer foundries). Due to the recession of semiconductorindustry in 1996, cycle time reduction to provide better customerservice becomes an even crucial issue for wafer foundries.It is commonly accepted that lot size reduction can shorten roduction cycle time. Due to constraints of conventional equipmentand technology, this concept did not widely applied in waferfabrication. However, because the progress of advanced technologies,restrictions of equipment and processes have been lessened in recent years. Wafer lot sizing policy thus becomes an alternativeand important method in reducing cycle time and deserves an extensive study. Therefore, instead of concentrating on the development of better scheduling methods or releasing and dispatching policies to reducecycle time in wafer fabrication, this research intents to achievethis goal through wafer lot sizing policies in which the bottleneckresource must be better utilized while non-bottleneck resources payallowable penalties in setup time and surplus capacity. This studyfirst analyzes the impact as well as the constraints of lot sizingpolicy on cycle time reduction for wafer fabrication. Global lot sizes at different utilization levels of critical equipment are suggested. The corresponding sensitivity analysis are made. Systemperformance influenced by batch equipment dispatching rules and the corresponding lot size policies are also studies.