Delay-dependent Power Estimation for Combibational Circuits
碩士 === 國立成功大學 === 電機工程學系 === 85 === In this thesis, We propose a time-efficient algorithm to estimate the power dissipation for delay-dependent combinational logic circuits. It can estimate the glitch effects at all nodes in the circuit under a general delay model without constructing global B...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67871269170050259646 |