Delay-dependent Power Estimation for Combibational Circuits
碩士 === 國立成功大學 === 電機工程學系 === 85 === In this thesis, We propose a time-efficient algorithm to estimate the power dissipation for delay-dependent combinational logic circuits. It can estimate the glitch effects at all nodes in the circuit under a general delay model without constructing global B...
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| Format: | Others |
| Language: | zh-TW |
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1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67871269170050259646 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 85 ===
In this thesis, We propose a time-efficient algorithm to estimate the power dissipation for delay-dependent combinational logic circuits. It can estimate the glitch effects at all nodes in the circuit under a general delay model without constructing global BDDs and without calculating Boolean difference for each possible transition time. By using the technique developed for the zero delay model; we can estimate the transition information of internal signals in about 1000 times shorter than simulation and maintain the average error in about 19％. The analysis of the running times of our approach indicates that it is applicable to large size circuits.
Considering the actual delay of logic gates, it can provide more closely power dissipation information for real circuits. Designers can find the dominate spurious power dissipation due to glitching and fix them in design phase.
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