The Architecture and Chip Implementation for Speech Recognition and Voice Compression Systems

• Main Authors: Suen, An-Nan, 孫安南
• Other Authors: Jhing-Fa Wang
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/94585011867419107779

博士 === 國立成功大學 === 資訊工程學系 === 85 === In this disserpation, the efficient and flexible VLSI architecture andimplementation for the voice word-recognizer and CELP voice compression systemare presented. In order to achieve a flexible and efficient VLSI realization,we use a programmable with specific core designstrategy which incorporates the best aspects of both programmable andapplication specific signal processors to achieve high speed, high accuracy,and efficient hardware realization for the speech applications.In this study, we present the CELP processor architectureand VLSI implementation. A programmable application-specific singlechip design for the CELP algorithm drastically reduces the cost andachieves real-time performance.In particular, the issues and accuracy study forthe fixed-point realization are also addressed herein.In order to speed up the codebook search, we also present a new classifieddynamic partial search structure for stochastic codebook of FS1016 CELP coderto replace the fixed partial search for selecting the best excitation vectorof stochastic codebook. In the proposed scheme, the conventional one-stagestochastic codebook search is substituted with a two-stage dynamic methodfor reducing the computational complexity without degrading the voice quality.We also propose the VLSI architecture and chip implementation for theFS1016 CELP decoder with reduced power and memory requirements. A singlechip implementation of the CELP decoder drastically reduces the cost andthe size of many CELP vocoder systems. Finally,a new LPC vocoder model based on forward-backward waveform prediction (FBLPC)for very low bit rate speech coding is presented. The FBLPC model only encodesand tranmits partial representative waveforms based on the mixed excitationLPC model. On the other hand, other partial waveforms which are not to beencoded and transmitted are reconstructed by an interpolating method calledforward-backward waveform prediction in the synthesis. This interpolatingmethod can decrease the bit rates rapidly, and the vocoder also can produceintelligible speech. A 1200bps FBLPC vocoder based on this model has beendesigned and implemented in real time.