Interrupt Control and Functional Simulation for The Pentium-pro and NSC98 Advanced Micro-Processor

• Main Authors: Yang, Ching-Yau, 楊景堯
• Other Authors: Chou Chun-Wen
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/98830021793289333450

碩士 === 逢甲大學 === 資訊工程研究所 === 85 === Abstract The NSC98 advanced microprocessor, being designed by NSC, is a high performance product and compatible with Intel X86 instruction CPU. It uses RISC processors in a flexible VLIW architecture; it converts each Intel X86 CISC instruction into one or more POP(Primitive Operations) RISC format instructions, and distributes 8 RISC instructions in each clock cycle to multiple execution unit. NSC98 is a 64-bit CPU, using a lot of brand new techniques for the structure of computer, such as super-scalar, branch prediction, instruction prefetch , speculative execution, dynamic scheduling, out-of-order execution and in-order completion. As the NSC98 advanced microprocessor executes several instructions at the same time, it is necessary to dispose the interrupted process precisely and to consider the complex condition when exception or interrupt occurs during instruction execution. This research will explore the overall details --- the interrupt classification, priority judgment, control process, circuit simulation and verification, and performance analysis of NSC98.According to the interrupt- trait of NSC98, this research will compare central and distributed interrupt handling methods, and in the end, we selected the central method . The exception and interrupt signals sent from NSC98 RAB and APIC will be arbitrated and treated by the exception/interrupt handler. And then, the Exception/Interrupt Handler will transmit signals to the decoder in the light of the priority, for maintaining the propriety of executing the order, and follow the process, the decoder will stop all instructions following the instruction of exception and interrupt, and then go on with executing them after the condition of exception and interrupt are serviced. In addition, there are two ways of executing the interrupt subroutine, i. e., single module execution or multiple module execution. The research will analyze the performance/cost ratio and the compatibility of single module execution with multiple module execution, and at last, chose the single module execution. Besides, to meet the target of NSC98 of 150MHz clock cycle, delay of any circuit path in the control unit must not exceed 6.7ns, For this purpose, all of the circuit functions must be completed within a clock cycle. Consequently, the complicated- design and high-speed circuit will substitutes the simple-design and low-speed one.For carrying out the design of this research, we will use Verilog to complete the RTL(Register Transistor Level) code, and simulate and prove circuit functions and efficiency. Finally, Cadence's Verilog in will be adopted for Placing and Routing, and estimate the layout area for the chip.