| Summary: | 碩士 === 逢甲大學 === 資訊工程研究所 === 85 === This thesis presents a high-speed signed residue number system
(RNS) multiplier which is derived from the early works of
unsigned RNS multipliers. The residue arithmetic function unit
has high-speed computation due to its natural parallelism. The
signed residue multiplication can be processed easily and
directly, unlike multiplication in binary number representation
which, beside multiplication, usually needs four additional
procedures, i.e., pre- and post- one's complement cycles, and
adding "1" to the pre- and post- one's complement cycles. In
RNS, signed multiplication can directly use the residue negative
operands, <(-x)>m or (m - x) as an input. The product result
is also automatically obtained, no pre- or post-procedures
needed. If the input is a binary form and negative, it can be
easily changed to the corresponding residue form by a converter.
Furthermore, the hardware structure of the signed RNS multiplier
is simple and is very suitable for VLSI implementation. In
addition, we have simulated and implemented an unsigned RNS
multiplier as a first step to implement the signed RNS
multipliers. We have simulated the design by C language,
Verilog-XL and Timemill, and the results are correct. And the
unsigned RNS multipliers have been implemented by Taiwan
Semiconductor Manufacture Company (TSMC) through the
recommendation of CHIP Implementation Center (CIC). And these
prototype chips have been tested and the functions have been
verified as well. The chip is implemented in 0.6 um CMOS SPDM
technology. Its size is 3.27205 mm * 3.29725 mm, its package is
48 pins, and it can operate at 50 MHz.
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