Efficient Simulation Alogorithm for Set-Associative Victim Cache Memory

碩士 === 中原大學 === 資訊工程學系 === 85 ===   Trace-driven simulation is the most commonly used technique for evaluating the behavior of a cache memory system. Prior to this investigation, all simulation algorithms were aimed at the conventional cache architecture without any extra device. This paper present...

Full description

Bibliographic Details
Main Author: 張延任
Other Authors: 張思恩
Format: Others
Language:en_US
Published: 1997
Online Access:http://ndltd.ncl.edu.tw/handle/81639848375032088617
id ndltd-TW-085CYCU3392014
record_format oai_dc
spelling ndltd-TW-085CYCU33920142015-10-13T12:15:14Z http://ndltd.ncl.edu.tw/handle/81639848375032088617 Efficient Simulation Alogorithm for Set-Associative Victim Cache Memory 集合關聯式受害者快取記憶體的高效率模擬演算法 張延任 碩士 中原大學 資訊工程學系 85   Trace-driven simulation is the most commonly used technique for evaluating the behavior of a cache memory system. Prior to this investigation, all simulation algorithms were aimed at the conventional cache architecture without any extra device. This paper presents 1) more efficient and easier one-pass algorithm for simulating alternative all-associativity (i.e. direct-mapped and set-associative) cache than early ones, 2) new and powerful one-pass algorithm for simulating alternative all-associativity caches with a victim cache of different entry member, and 3) uses those simulation results to compare set-associative caches and direct-mapped caches with a small victim cache from various aspect.   First, we propose a more efficient algorithm, called hash-like RM simulation, for simulating alternative caches with the same block size, and using the LRU replacement policy, with a single pass through an address trace. This algorithm facilitates more rapid simulation of alternative caches by reducing the average search depth in fully stack. And further, we develop a powerful algorithm, victim one-pass simulation, for simulating alternative caches with a victim cache (buffer) of different entry number in one pass. Since the behavior of victim cache is detrimental to one-pass simulation, this algorithm is more complicated than those for simulating memory system without victim cache.   Finally, our experimental data provide evidence that adding a victim cache is worthless for direct-mapped instruction caches with size more than 32K, but 64K direct-mapped data caches with a 4-6 entries victim cache can compete in miss ratios with those of 64K 2-way set-associative caches and have the more superior average memory access time. 張思恩 1997 學位論文 ; thesis 84 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 中原大學 === 資訊工程學系 === 85 ===   Trace-driven simulation is the most commonly used technique for evaluating the behavior of a cache memory system. Prior to this investigation, all simulation algorithms were aimed at the conventional cache architecture without any extra device. This paper presents 1) more efficient and easier one-pass algorithm for simulating alternative all-associativity (i.e. direct-mapped and set-associative) cache than early ones, 2) new and powerful one-pass algorithm for simulating alternative all-associativity caches with a victim cache of different entry member, and 3) uses those simulation results to compare set-associative caches and direct-mapped caches with a small victim cache from various aspect.   First, we propose a more efficient algorithm, called hash-like RM simulation, for simulating alternative caches with the same block size, and using the LRU replacement policy, with a single pass through an address trace. This algorithm facilitates more rapid simulation of alternative caches by reducing the average search depth in fully stack. And further, we develop a powerful algorithm, victim one-pass simulation, for simulating alternative caches with a victim cache (buffer) of different entry number in one pass. Since the behavior of victim cache is detrimental to one-pass simulation, this algorithm is more complicated than those for simulating memory system without victim cache.   Finally, our experimental data provide evidence that adding a victim cache is worthless for direct-mapped instruction caches with size more than 32K, but 64K direct-mapped data caches with a 4-6 entries victim cache can compete in miss ratios with those of 64K 2-way set-associative caches and have the more superior average memory access time.
author2 張思恩
author_facet 張思恩
張延任
author 張延任
spellingShingle 張延任
Efficient Simulation Alogorithm for Set-Associative Victim Cache Memory
author_sort 張延任
title Efficient Simulation Alogorithm for Set-Associative Victim Cache Memory
title_short Efficient Simulation Alogorithm for Set-Associative Victim Cache Memory
title_full Efficient Simulation Alogorithm for Set-Associative Victim Cache Memory
title_fullStr Efficient Simulation Alogorithm for Set-Associative Victim Cache Memory
title_full_unstemmed Efficient Simulation Alogorithm for Set-Associative Victim Cache Memory
title_sort efficient simulation alogorithm for set-associative victim cache memory
publishDate 1997
url http://ndltd.ncl.edu.tw/handle/81639848375032088617
work_keys_str_mv AT zhāngyánrèn efficientsimulationalogorithmforsetassociativevictimcachememory
AT zhāngyánrèn jíhéguānliánshìshòuhàizhěkuàiqǔjìyìtǐdegāoxiàolǜmónǐyǎnsuànfǎ
_version_ 1716855931127463936