| Summary: | 碩士 === 國立中正大學 === 電機工程學系 === 85 === AbstractThe development and widespread use of digital
transmission, in combination with digital switching, has led to
all-digital networks that require timing and synchronization.
This thesis is concerned with the design of the Timing
Generation Unit (TGU) in digital transmission system
application. A digital Phase Locked Loop (PLL) is presented,
which consists of external reference input, jitter reduction
loop, and microprocessor-controlled PLL. We use PLL technique to
improve timing impairments.In this thesis, the hardware of
microprocessor-controlled PLL has been designed and implemented.
The application of FPGA device and D/A converter is included. An
algorithm for the microprocessor-controlled PLL subsystem is
proposed. For future research, one has to implement the
algorithm and verify the functions of the microprocessor-
controlled PLL subsystem.
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