Low-Power Cell-Based VLSI Design Using Cell Replacement Techniques
碩士 === 國立中正大學 === 電機工程學系 === 85 === Low-power design is an important trend in VLSI development. The designturn-around time of VLSI can be shorten by utilizing the cell-based designstyle. Embedding low-power design techniques into the ce...
Main Authors: | Wang, Jei-Chien, 王瑞乾 |
---|---|
Other Authors: | Wang Jinn-Shyan |
Format: | Others |
Language: | zh-TW |
Published: |
1997
|
Online Access: | http://ndltd.ncl.edu.tw/handle/41464856018916736533 |
Similar Items
-
An Implementation of Integrable Low Power Techniques for Modern Cell-Based VLSI Design
by: Lee Ming Chung, et al.
Published: (2005) -
Timing Driven Quadrisection Partition-Based Standard Cell Placement VLSI Design
by: Jei-Ming Feng, et al.
Published: (2003) -
Low-power analogue VLSI cochlear implants : approaches and design techniques
by: Machado, Gerson Augusto Salado
Published: (1997) -
Optimization Techniques for Low Power and Process Variations in VLSI Circuit Designs
by: Chen, Po-Yuan, et al.
Published: (2009) -
Implementation Techniques of Segmented Bus Design for Low-Power VLSI Chips
by: I-Oing Hsu, et al.
Published: (1998)