Low-Power Cell-Based VLSI Design Using Cell Replacement Techniques

• Main Authors: Wang, Jei-Chien, 王瑞乾
• Other Authors: Wang Jinn-Shyan
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/41464856018916736533

碩士 === 國立中正大學 === 電機工程學系 === 85 === Low-power design is an important trend in VLSI development. The designturn-around time of VLSI can be shorten by utilizing the cell-based designstyle. Embedding low-power design techniques into the cell-based designenvironment owns the advantages of accelerating the IC development, savingthe development cost, and improving the design efficiency. This thesis focus on the study of how to reduce the power dissipationin the logic/circuit level of abstract of a cell- based VLSI designenvironment. A new style of standard cells with dual power-supply rails is proposed,and the corresponding cell library is developed in the cooperation of myclassmate doing the same project. An EDA program, called CRISP (CellReplacement Intended to Squeeze Power), is also developed to help theutilization of the new cell library more efficiently. CRISP has beenintegrated into an existing VLSI design environment. By analysis of CRISP,some gates on non-critical paths can be replaced by those gates with lowerdriving capability or by those gates supplied with lower power-supply voltageto save power consumption. The main features of CRISP include (1)integratedinto the existing VLSI design environment, (2)breaking the limitation ofclustered voltage scaling, (3)suitable to sequential circuits, and(4)adopting more accurate nonlinear timing and power models. Benchmark circuits of ISCAS85 and ISCAS89 have been analyzed by CRISPusing the newly developed cell library. The average power consumptionreduction is about 23%, and the maximum power reduction can even reaches 45%for some cases. The new standard cells have been used in an experimentalmicro-controller chip. The chip has been processed, packaged, and testedsuccessfully.