| Summary: | 碩士 === 大同工學院 === 資訊工程學系 === 84 === Because CPU speeds continue to increase faster than either DRAM
access times or disk access times, memory will increasingly be a
factor that limits performance. Overcoming the growing gap
between CPU speeds and lower levels of the hierarchy is
currently the topic of much research. One potential solution
is to increase the number of levels in the hierarchy,
using two-level caches. Most manufacturers put the first-
level caches on the processor chip and leave the second-
level cache on the processor board. An external
cache can improve the performance by providing a larger
cache. But its off-chip implementation makes it slower.
To reduce the time needed for data to move from
the external cache to the processor, we decide to use a
two-level on-chip cache hierarchy solution for a more
aggressive processor than Intel's P6 processor.
The new processor should allow 150-MHz speed grade.
Here we design a second-level on-chip cache controller.
The cache controller is configured to support a 256-KByte,
4-way set associative, write-through cache. The cache line width
is 256 bits or 32 bytes.
We develop two models of the cache in Verilog HDL.
The first model we design is an algorithmic level abstraction.
The second model we write is at the register-transfer level.
All the models have been simulated using
the Verilog-XL 2.2.1 simulator.
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