| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 84 === In digital communications, correct timing is necessary to reduce
the ISI in the receiver. We adopt a timing recovery scheme using
the Gardner''s timing error detector, a novel digital loop filter
and a digital controlled oscillator to generate the optimal
sampling clock. The Doppler drift owing to vehicle movement and
the frequency difference between local oscillator and carrier
will result in a frequency offset in the receiver. The
frequency offset will cause a phase rotation in the signal after
demodulation and degrade the system performance. A baseband
feedback frequency offset compensator is used to improve the
performance. In TDMA system, the user''s data stream is organized
into uniformly-sized groups of bits. For a receiver to detect
the incoming data stream, the sampling clock must be
synchronized with the data stream''s frame structure. We use a
simple structure to implement the frame synchronization. In this
thesis, timing recovery, frequency offset compensation and frame
synchronization are integrated together and implemented by VLSI
design using 0.8um silicon process. The total chip size is
3894.2um x 3867.2um. The symbol rate can be at least 3M symbols/
sec.
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