| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 84 === GPS signal acquisition in high dynamic environments requires
fast identification of the incoming signal's frequency and PN
code phase offsets that lies in very large uncertaintyregion.
The presence of data modulation makes the acquisition problem
even more difficultto deal with. This thesis proposes a new
detection scheme suitable for acquiring the GPS signal in such
an environment. Coherent complex integration of the received
waveform withthe local PN coded signal is performed. The
integration outputs are differentially detected andthe detected
samples are accumulated, the magnitude of the resulting sum is
then used as thetest variable for deciding if the current
frequency/code phase offsets are the correct estimates.This
detector like the conventional square-law combining detector can
beimplemented by FFTs. The operation characteristic of the
proposed detector is analyzed and the analytic results are shown
to be consistent with computer simulations. Numerical results
show that, compared with the square-law combining detector, our
new detector is more robust against thermal noise and Doppler
shift but, in a few cases, also more sensitive to the presence
of data modulation.Both the new and the conventional detectors
are applied to three code acquisition systems and the associated
performances are compared. These three systems are (i) the fully
parallel system, (ii) the two-dwell parallel system, and (iii)
the (two-dwell) parallel-serial system.The latter two systems
have two phases: the coarse acquisition phase and the fine
acquisitionphase. The first phase uses larger frequency bin
width and code phase step size, poorer frequency resolution
results because it employs a shorter coherent integration time.
The second phase searches the one chosen by thefirst phase plus
a small neighboring region. First-order (mean), second-order
(standard deviation) and complete statistics (pdf and cdf) of
the code acquisition time for the latter two systems (those for
the first system are trivial and are omitted) are obtained.
Tradeoff between hardware complexity and performance is
discussed. System parameters are optimizedand performance are
compared. When the cost of hardware is not considered,the fully
parallel architecture yields the fastest mean acquisition time
performance. For both parallel and parallel-serial systems, the
mean acquisition time is a linear function of the system
complexity (the product of the numbers of the detectors and FFT'
s). With a reasonable hardware constraint, the proposed scheme
does provide performance that is superior to that of the systems
using conventional square-law combining detector.Our calculation
also show that the new detector serves our application well--it
yieldsexcellent acquisition performance with an affordable
complexity.
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