rogramable 1.28Ghz wideband frequency divider module

碩士 === 國立交通大學 === 電信工程研究所 === 84 === In this thesis we design a wideband, lower phase noise frequency dividermodule that phase noise is as low as -130dBc/Hz(offset 10KHz)and generate a 640MHz local oscillator to support mixer generating100K...

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Main Authors: Teng, Gingfu, 鄧錦福
Other Authors: Christina Chou
Format: Others
Language:zh-TW
Online Access:http://ndltd.ncl.edu.tw/handle/62981483875175472058
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spelling ndltd-TW-084NCTU04350022016-02-05T04:16:37Z http://ndltd.ncl.edu.tw/handle/62981483875175472058 rogramable 1.28Ghz wideband frequency divider module 可程式化寬頻除頻器模組 Teng, Gingfu 鄧錦福 碩士 國立交通大學 電信工程研究所 84 In this thesis we design a wideband, lower phase noise frequency dividermodule that phase noise is as low as -130dBc/Hz(offset 10KHz)and generate a 640MHz local oscillator to support mixer generating100KHz~160MHz. Frequency is covered from 100KHz extend to 1280MHz.Module include some frequency divider, high Q filters, control switches,wideband amplifiers, frequency doublers, voltage control oscillator(VCO).After finishing all component's design and test, we try to integrate itand generate a high performance, high Q signal. In frequency divider module, we test NEC compant's UPB581, UPB584, UPB565, GEC Plessey's SP8605 frequency dividers and compare its phase noise and output power. We design and compare elliptical and chebyshevfonts low pass filters(LPF) in the high frequency's response. LPF willisolate signal 40dBc in the stop band and pass signal in the pass band.Design a narrow bandwidth band pass filter(BPF) to reject the unwanted signal. Design single pole double throw(SPDT) and SP3T switch. We compare4 style SPDT's loss and isolation then choose the best one to our controlcomponent. We design a 10dB gain, matched 160~640MHz wideband amplifier to compensate system gain and a high gain, matched 640MHz amplifier to driver local oscillator 640MHz to 7 dBm. To generate 640MHz oscillator, we use two methods to achieve it.One use a stable, precision 40MHz multiplier 4 times and cascade BPFto reject high order harmonics and fundamental signal to get 640MHz.In this method, we design a module that power is 7dBm, phase noise is-104dB(10KHz offset). In another method, we design a common Emitter VCO and program synthesizer to generate a high Q, low phase noise640MHz oscillator. For this method, we also design a module that power is 7.5dBm, phase noise is -104 dBc/Hz(10KHz offset). Christina Chou 周復芳 學位論文 ; thesis 108 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立交通大學 === 電信工程研究所 === 84 === In this thesis we design a wideband, lower phase noise frequency dividermodule that phase noise is as low as -130dBc/Hz(offset 10KHz)and generate a 640MHz local oscillator to support mixer generating100KHz~160MHz. Frequency is covered from 100KHz extend to 1280MHz.Module include some frequency divider, high Q filters, control switches,wideband amplifiers, frequency doublers, voltage control oscillator(VCO).After finishing all component's design and test, we try to integrate itand generate a high performance, high Q signal. In frequency divider module, we test NEC compant's UPB581, UPB584, UPB565, GEC Plessey's SP8605 frequency dividers and compare its phase noise and output power. We design and compare elliptical and chebyshevfonts low pass filters(LPF) in the high frequency's response. LPF willisolate signal 40dBc in the stop band and pass signal in the pass band.Design a narrow bandwidth band pass filter(BPF) to reject the unwanted signal. Design single pole double throw(SPDT) and SP3T switch. We compare4 style SPDT's loss and isolation then choose the best one to our controlcomponent. We design a 10dB gain, matched 160~640MHz wideband amplifier to compensate system gain and a high gain, matched 640MHz amplifier to driver local oscillator 640MHz to 7 dBm. To generate 640MHz oscillator, we use two methods to achieve it.One use a stable, precision 40MHz multiplier 4 times and cascade BPFto reject high order harmonics and fundamental signal to get 640MHz.In this method, we design a module that power is 7dBm, phase noise is-104dB(10KHz offset). In another method, we design a common Emitter VCO and program synthesizer to generate a high Q, low phase noise640MHz oscillator. For this method, we also design a module that power is 7.5dBm, phase noise is -104 dBc/Hz(10KHz offset).
author2 Christina Chou
author_facet Christina Chou
Teng, Gingfu
鄧錦福
author Teng, Gingfu
鄧錦福
spellingShingle Teng, Gingfu
鄧錦福
rogramable 1.28Ghz wideband frequency divider module
author_sort Teng, Gingfu
title rogramable 1.28Ghz wideband frequency divider module
title_short rogramable 1.28Ghz wideband frequency divider module
title_full rogramable 1.28Ghz wideband frequency divider module
title_fullStr rogramable 1.28Ghz wideband frequency divider module
title_full_unstemmed rogramable 1.28Ghz wideband frequency divider module
title_sort rogramable 1.28ghz wideband frequency divider module
url http://ndltd.ncl.edu.tw/handle/62981483875175472058
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