| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 84 === In the thesis, post-processing of 3D Graphic Rendering
Processor (3DGP) is studied. A proposed architecture for 3DGP is
implemented, which includes the operations related to stencil, Z
and RGBA buffers. The charcateristics of various RAM (Random
Access Memory) chips are analyzed, then BEDO DRAM and VRAM are
choosen for frame buffer storage. Finally, the designs written
in Verilog HDL are synthesized by Synopsys using PHILIPS' cell
library which is based on 3.3V, 0.5um, triple-metal
semiconductor technology.The results of simulation show that the
peak performance of local buffer is 20M pixels/sec, and RGBA
buffer is 5M pixels/sec.
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