Area-Efficient Layout Design for Output and Input Buffers to Improve Driving Capability and ESD Robustness of CMOS VLSI
碩士 === 國立交通大學 === 電子研究所 === 84 === In this thesis, we propose three new layout designs of output and input buffers of CMOS IC''s. While the CMOS technology has been scaled down into deep-submicron regime with thinner gate oxide, shorter channel...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/38572546648099296051 |