The Design and Analysis of Low-Voltage CMOS Algorithmic A/D Converter

• Main Authors: Lai, Horng-Goung, 賴宏光
• Other Authors: Chung-Yu Wu, Ping-Hsing Lu
• Format: Others
• Language: zh-TW
• Published: 1996
• Online Access: http://ndltd.ncl.edu.tw/handle/45426325282698692402

碩士 === 國立交通大學 === 電子研究所 === 84 === The fast growing application of personal data processing and communication systems as well as the inherent device miniaturization has driven the CMOS ULSI ( Ultra Large Scale Integrated circuit ) toward lower-voltage operation. The scaled- down power supply voltages are from 5V, through 3.3V, toward 2V, and ultimately to 1V. Under this scaling trend, both digital and analog integrated circuits, particularly the mixed analog/ digital ULSI signal processing systems, should be designed by using the low supply voltage as well as the submicron CMOS devices.This thesis has proposed a new design technique to design a low-voltage operational amplifier using the n-well PMOS device with positive substrate bias. Using the proposed design technique and the low-voltage CMOS Op Amp, a capacitor-ratio- independent and gain-insensitive algorithmic analog-to-digital converter at 1.2V power supply voltage is analyzed and designed. It consists of operational amplifiers, comparators, latch, and clock booster which have been designed associated with the novel techniques for low supply-voltage operation. The configuration of this algorithmic analog-to-digital converter is inherently insensitive to capacitor ratio accuracy as well as the finite gain and the offset voltage of the operational amplifiers. Therefore, the switching error is the major error source. With fully differential configuration, it is suitable for 1.2V low voltage operation. The simulated results have shown that this algorithmic A/D converter can achieve 8 bit resolution at 1.2V supply voltage with 1.10mW power consumption. Furthermore, the proposed Op Amp and A/D converter have been fabricated with the 0.8(m n-well DPDM CMOS process with doubled poly linear capacitor. The experimental result shows that the proposed Op Amp has a dc gain of 50dB, unity-gain frequency of 2MHz, CMRR about 50dB and slew rate is 2V/(sec.