| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 84 === Subthreshold CMOS mismatch analysis is one of the most
important issues in the low power, low voltage field. We have
measured the current mismatch of identically drawn p- and n-type
MOSFETs (similar to current mirror) operating in subthreshold or
weak inversion to above-threshold regions with different gate
width-to-length ratios, transistor spacing distances, and layout
orientations. These transistors were characterized with back-
gate reverse and forward biases. The first observation is that
devices operating in subthreshold region exhibit larger mismatch
than those in above-threshold region. This is due to the
exponential dependence of current on gate and bulk voltages as
well as process parameters. In the case of back-gate reverse
bias, we have found that current mismatch increases as the
magnitude of back-gate reverse bias increases. On the other
hand, with the supply of back-gate forward bias, the current
mismatch decreases with increasing the back-gate bias in all
operation regions. With the data measured from devices with
difference sizes, spacing distances, and layout orientations, we
have found that (i) small size devices not only exhibit larger
mismatch, but also are more sensitive to back-gate bias; (ii) p-
type MOSFET exhibits larger mismatch and less sensitive to back-
gate bias than n-type MOSFET; and (iii) drawing transistors
closely and in horizontal orientation improves the match. We
have also derived an analytical statistical model that has
successfully reproduced the mismatch data in weak inversion for
different back-gate biases and device dimensions. With this
model, the current mismatch can be expressed as a function of
the variations in process parameters, namely, flat-band voltage
and body effect coefficient. The extracted process variations
are shown to appropriately follow the inverse square root of the
device area.
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