| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 84 === 3-D Computer graphics has played an important role in
multimedia and virtual reality systems. Up to the beginning
ofthe 1990s, applications of 3-D graphics emerge rapidly from
technical areas to non-technical areas. Therefore the goal of
state-of-the-art 3-D graphics hardware design not only focus on
high performance and quality, but also low cost and system
integration. In this thesis, a 3-D graphics processor is
proposed to improvethe rendering performance, and the hardware
of rasterizationunit with antialiasing capacity is designed. By
making use ofthe parallelism in pixel data, the system block of
3-D graphics processor is analyzed to reduce the redundant
internal bus routing and registers. The DDA (Digital
Differential Analyzer) operation and antialiasing are both the
time critical units in the hardware design for rasterization. To
improve the time critical condition, we develop two architecture
designs: The first is self carry routing adder (SCRA) for DDA
operations. The DDA operations suffer the low hardware
utilization caused by the various lengths of add operations. By
segmentation, rearrangement and dynamic carry routing, The SCRA
design can reduce the delay time (10.51ns in 0.03pf load) and
raise the hardware utilization (92.93%). The second is the sub-
scanline antialiasing algorithm for real-time antialiasing. The
delay time is reduced (7.6ns in 0.03pf load) and only moderate
area is necessary. All design for this 3-D graphics processor is
based on the 0.5 um CMOS cell library of Philips.
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