Research on Performance Enhancements for Limited-Directory Cache Coherence Protocol
碩士 === 國立交通大學 === 資訊科學學系 === 84 === Caches enhance the performance of multiprocessors by reducing average memoryaccess latency, but caches in a multiprocessing environment also introduce the cache coherence problem.Cache coherence protocol...
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| Format: | Others |
| Language: | zh-TW |
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1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/16425197330042575572 |