Design and Analysis of Directory-Based Cache Coherent Multistage Interconnection Networks

• Main Authors: Liu, Guan-Ting, 劉冠廷
• Other Authors: Chuang Jen-Hui
• Format: Others
• Language: zh-TW
• Published: 1996
• Online Access: http://ndltd.ncl.edu.tw/handle/32456335593574748628

碩士 === 國立交通大學 === 資訊科學學系 === 84 === Multistage Interconnection Networks (MIN's) are known to be highly scalableand fault tolerent structures for large multi- processor interconnections. Theconventional MIN's switches do not support cache coherence protocols efficiently due to the lacks of a fast broadcasting medium and cache coherentdirectory information. In this paper, we introduce a directory of cache linestate information into the lowest level Min's switches each connects a clusterof processors. A multiple shared cache coherence protocol is developed to usethis directories scheme to reduce the network traffic for cache coherencebetween the clusters of processors. Analytical model for this cache coherentarchitecture is also developed.