Total Wire Length and Performance Optimization for Field Programmable Gate Array Technology Mapping
碩士 === 國立成功大學 === 電機工程研究所 === 84 === This thesis focuses on solving the technology mapping problem of the type of FPGAs that use lookup tables to implement logic functions. The technology mapping is to transform a mutli-level Boolean network into a Config...
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| Format: | Others |
| Language: | en_US |
| Published: |
1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67747841222444320964 |