| Summary: | 碩士 === 中原大學 === 電子工程學系 === 84 === In this paper, we propose a logic circuits design method using
EXOR as based gates. A heuristic simplification algorithm for
ESOP with two-valued inputs multiple-output functions is the
center of this paper. Minimization of ESOP corresponds to
reduces the number of the products as the first objective, and
then reduces the number of the literals as the second
objective. We use a PCRM (permissible-cube-related minterm)
graph to generate and locate permissible cubes which are
required for initial solutions of ESOP. For each pair of
products, the deve- loped EXOR rules are applied iteratively.
The simplification algorithm provide a nearly optimal ESOP
expression which can have the minimum number of products and
literals. Finally, we use a AND-EXOR PLA with two-bit decoders
to implement the circuits. We will prove that AND-EXOR
expressions require fewer pro- ducts and literals than AND-OR
expressions to realize randomly generated Boolean functions.
This shows the two-level realiza- ation based on the ESOP
require fewer gates and connections than on based on the SOP.
At the same time, by introducing two-bit decoders, we can often
reduce the number of the products. Compared to traditional
method for AND-OR simplification, we simplify many arithmetic
circuits by our simplification algo- rithm. In most cases, we
obtain a near-minimum solutions. In this paper, we also
describe an application of the EXOR gates to near-optimal logic
circuits design for decoded PLA's. Therefore, there are two
logic design methods that can be used to reduce the area
required by a EXPLA. First, we can reduce the number of the
products in ESOP. Second, we can use two-bit rather than single-
bit decoders.
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