| Summary: | 碩士 === 國立臺灣科技大學 === 工程技術研究所 === 83 === L去十年來,VLSI 技術快速發展, 類比電路積體化的趨勢愈加明顯,而以
CMOS 為架構設計的電路更是類比電路邁向積體化最重要的關鍵。因此,
本論文將依據 MOSFET 電晶體操作在飽和 (saturation) 區與三極體
(triode) 區的數學模式設計一些類比信號處理系統中常用的線性
linear) 非線性 (nonlinear) 功能的新型電路。在非線性電路方面有電
壓向量加法器 (vector summation) 與除法器 (divider); 線性方面則
包含電壓控制轉導放大器 (voltage-controlled
operational ransconductance amplifier, OTA) 、 電壓控制浮接電阻
器 (voltage - ontrolled floating resistor) 與電流傳輸器
(current onveyor,CCII)等。在電路功能驗証方面, 我們採用 Meta-
Software 公司的 HSPICE evel 3 參數執行模擬工作, 另外以 CD4007
電晶體陣列作面板上實驗, 並利用 CADENCE 公司開發的 OPUS IC 設
計系統軟體, 經由國科會多計劃晶片 (MPC) 協助電路實現。
ce rapid advances in silicon VLSI (very-large-scaled
integration) technology in the past decade, the trend
for integrating analog circuits and the circuit architectures
based on CMOS technology become more important. In this thesis,
several linear and nonlinear CMOS circuits are proposed.
These kinds of circuits are widely used in analog signal
processing systems and designed based on the mathematical
models of MOSFET operating in saturation and triode
regions, respectively. The linear circuits designed in this
thesis are voltage-controlled operational transconductance
amplifier (OTA), voltage-controlled floating resistor, and
current conveyor (CCII) while the nonlinear circuits are
voltage-mode vector summation and divider circuits. To
verify our idea and designs of the proposed circuits, the
level 3 parameters of HSPICE from Meta-Software are used to
do the simulations for all circuits.Moreover, to emphasize the
idea of our designs, some are also implemented with
discrete CMOS transistor arrays (CD4007). Finally, the
layouts of these circuits in this thesis are generated by
using the OPUS IC design system from CADENCE and submitted
to CIC (Chip Implementation Center) for realizing the final
ICs.
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