The design of a low-power RISC CPU for PDA

碩士 === 國立臺灣大學 === 電機工程學研究所 === 83 ===

Bibliographic Details
Main Authors:	Yu, Pei, 喻珮
Other Authors:	Lai, Fei Biao
Format:	Others
Language:	zh-TW
Published:	1995
Online Access:	http://ndltd.ncl.edu.tw/handle/04784417396033425292

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spelling	ndltd-TW-083NTU024421832016-07-15T04:12:43Z http://ndltd.ncl.edu.tw/handle/04784417396033425292 The design of a low-power RISC CPU for PDA 個人數位助理適用之省電型精簡指令集中央處理器設計 Yu, Pei 喻珮碩士國立臺灣大學電機工程學研究所 83 Lai, Fei Biao 賴飛羆 1995 學位論文 ; thesis 0 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立臺灣大學 === 電機工程學研究所 === 83 ===
author2	Lai, Fei Biao
author_facet	Lai, Fei Biao Yu, Pei 喻珮
author	Yu, Pei 喻珮
spellingShingle	Yu, Pei 喻珮 The design of a low-power RISC CPU for PDA
author_sort	Yu, Pei
title	The design of a low-power RISC CPU for PDA
title_short	The design of a low-power RISC CPU for PDA
title_full	The design of a low-power RISC CPU for PDA
title_fullStr	The design of a low-power RISC CPU for PDA
title_full_unstemmed	The design of a low-power RISC CPU for PDA
title_sort	design of a low-power risc cpu for pda
publishDate	1995
url	http://ndltd.ncl.edu.tw/handle/04784417396033425292
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The design of a low-power RISC CPU for PDA

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