Design and implementation of low-power phase-locked loop in time-division multiple-access receiver

碩士 === 國立臺灣大學 === 電機工程學研究所 === 83 ===

Bibliographic Details
Main Authors:	Cheng, Yong Xin, 程永信
Other Authors:	Feng, Wu Xiong
Format:	Others
Language:	zh-TW
Published:	1995
Online Access:	http://ndltd.ncl.edu.tw/handle/55516945897615614880

id	ndltd-TW-083NTU02442107
record_format	oai_dc
spelling	ndltd-TW-083NTU024421072016-07-15T04:12:43Z http://ndltd.ncl.edu.tw/handle/55516945897615614880 Design and implementation of low-power phase-locked loop in time-division multiple-access receiver 分時處理通訊系統之接收器的低功率鎖相回路之設計與實現 Cheng, Yong Xin 程永信碩士國立臺灣大學電機工程學研究所 83 Feng, Wu Xiong 馮武雄 1995 學位論文 ; thesis 0 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立臺灣大學 === 電機工程學研究所 === 83 ===
author2	Feng, Wu Xiong
author_facet	Feng, Wu Xiong Cheng, Yong Xin 程永信
author	Cheng, Yong Xin 程永信
spellingShingle	Cheng, Yong Xin 程永信 Design and implementation of low-power phase-locked loop in time-division multiple-access receiver
author_sort	Cheng, Yong Xin
title	Design and implementation of low-power phase-locked loop in time-division multiple-access receiver
title_short	Design and implementation of low-power phase-locked loop in time-division multiple-access receiver
title_full	Design and implementation of low-power phase-locked loop in time-division multiple-access receiver
title_fullStr	Design and implementation of low-power phase-locked loop in time-division multiple-access receiver
title_full_unstemmed	Design and implementation of low-power phase-locked loop in time-division multiple-access receiver
title_sort	design and implementation of low-power phase-locked loop in time-division multiple-access receiver
publishDate	1995
url	http://ndltd.ncl.edu.tw/handle/55516945897615614880
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Design and implementation of low-power phase-locked loop in time-division multiple-access receiver

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