VLSI Implementation of an On-Line Redundant CORDIC with Constant Scale Factor Using Double Rotation Method

• Main Authors: Lin Jung Chun, 林榮俊
• Other Authors: Hsiao, S.F.
• Format: Others
• Language: zh-TW
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/17588886216640761779

碩士 === 國立中山大學 === 資訊工程研究所 === 83 === The CORDIC ( COordinate Rotation DIgital Compuetr ) algorithm is widely used for digital signal prcosessing, matrix computation,image and graphic applications.It is suitable for VLSI implementation. We can use the pipeline architecture instead of iterative calculation structure to increase the throughput of CORDIC. The redundant adder is also used to replace the conventional adder in order to speed up the addition operations and thus improve the clock rate. Comparing the redundant number representation with the 2's complement representation,the former eliminates the carry propagation problem.So we use the redundant adder instead of the conventional adder to increase the speed of the CORDIC processor.But it will cause the nonconstant scaling factor. So we use double rotation CORDIC-a variant of CORDIC-to keep the scaling factor constant.Using the redundant number property,we can add two operands from MSD(Most Significant Digit)and use the digit on-line method to realize the addition with much less hardware area compared to the word-parallel version.