Design of four-PEs video signal processor

• Main Authors: TU, JUN AN, 涂俊安
• Other Authors: WEN, HUAI AN
• Format: Others
• Language: en_US
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/80378060542601820663

碩士 === 國立交通大學 === 電子研究所 === 83 === In this thesis, we present a programmable video signal processor which includes four parallel-pipelined processing units, named 4P-VSP. Using the designed datapath architectures, all processing units and storage units can operate concurrently and it is suitable for many video algorithm applications. Moreover, we also designed some vector instructions for the 4P-VSP to support vector- type, accumulation-type and accumulation-with-MMD-type processing modes to increase the execution efficiency in video applications. It has been shown that the performance can be improved more than 5 times via using the designed vector instructions. The 4P-VSP is designed with 0.8um CMOS TSMC''S technology. In consideration of future implementations, gate- level description is adopted in all modules, based on the timing characteristics of CCL08-V1.0 Standard-Cell Library, the 4P-VSP has been verified via Verilog-XL simulation. Under the system clock of 36MHz, the maximum performance is 1214-MOPS and the maximum data throughput rate is about 55M bits/s. The 4P-VSP contains about 580k transistors and the layout of each function block has been done by using Cadence tools.