Implementation of Redundant CORDIC Processor with Efficent Variable Scale Factor Compensation

• Main Authors: Jurcy Hwang, 黃焯熙
• Other Authors: Sau-Gee Chen
• Format: Others
• Language: zh-TW
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/56840721823982786273

碩士 === 國立交通大學 === 電子研究所 === 83 === CORDIC演算法為許多基本數學運算提供了快速的計算方式。在本篇論 中 ，我們提出了以on-line 的方式與座標及角度運算同步計算比例因數 scaling factor ）分解的 Radix-2 Redundant CORDIC 架構以解決此顐 狾]數數必須保持為常數的困擾。比例因數的分解乃藉由計算指數函數漱 隤k求得的，將比例因數分解成Σln(l+s*2^(-i))(radix-2）並以檢查怜 玫X位元來簡單估計 s，如此我們可以簡單快速且小面積的電路計算之A方 向參數的計計亦同。在比例因數補償方面我們提出三種方法：①在所釭漕 井蚺峸y標算算結束之後再做移位和加法的運算；②每個遞迴運算結纁犮 艅韐N做移位和加法的運算；③將比例因數 on-line計算出來並且在井蚺 峸y標運算結束後以乘法器完成計算。另外由於比例因數可以是變數A我們 將此　Radix-2 Redundant CORDIC 演算法推展至 Radix-4 以減少摯j運 算的次數及加速 CORDIC 的運算和減低成本。最後我們以新的演算k為基 礎使用 CCL standard cell與CADENCE's tool設計了radix-2 的旋鉏狾★ q路，並送至 CIC 製成晶片，此晶片速度33MHz，約有9000個邏輯h，面積 約為5120μmx 4740μm。 In this work, an efficient variable scale factor compensation for the redundant CORDIC is discussed. The compensation scheme transforms the complicated variable scale factor problem introduced in using redundant CORDIC into a sequence of simple shift-and-add operations. The resulted CORDIC enjoys both fast speed in rotation iteration as well as high speed and low overhead scale factor compensation which is difficult for existing redundant CORDICs. With the on-line variable scale factor decomposition, we discuss three scale factor compensation schemes which are tailored for better cost/ performance consideration for different hardware realization strategies. We also extend the radix-2 redundant CORDIC and variable scale factor compensation algorithms to a radix-4 version for better speed and area performance consideration. Finally the algorithm is VLSI implemented as a rotation-mode CORDIC processor by using CCL standard cells and CADENCE's tools. The CORDIC chip layout has been sent to CIC for chip realization. The chip has a 33MHz clock rate, 9000 gates, and a area of 5142um x 4123um.