CMOS/SOI Device Simulation:Accumulation Mode vs.Enhancement Mode

• Main Authors: C.B.Cheng, 鄭召寶
• Other Authors: S.C.Sun,M.C.Chen
• Format: Others
• Language: en_US
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/84418223502980781303

碩士 === 國立交通大學 === 電子研究所 === 83 === Silicon on insulator (SOI) technology is a promising candidate for future ULSI as the quality of SOI material continues to improve. Thin (less than 1000A) SOI film thickness which makes fully depleted SOI MOSFETs is important for minimization of short channel effects, easy isolation, elimination of latch-up, steeper subthreshold slopes, and increased current drive capability which will make low power and high speed devices work well. The purpose of this research is to investigate: A. the dependence of fully depleted SOI as the devices are scaled down to deep submicron area. Three key parameters: (1). The threshold voltage (2). Subthreshold swing (3). Current drive capability B. the scaling rule of CMOS/SOI. Si film thickness, gate oxide thickness , channel length, and channel doping will be the key parameters in this investigation. 2D device simulator is used in device optimization and in gaining insight of physical mechanism.