Trade-offs in Video Coder VLSI Design
碩士 === 國立交通大學 === 電子研究所 === 83 === This thesis is focused on the system-level design of the image compression coder chip for the CCITT H.261 standard. An H.261 coder consists of several operation units such as motion estimation, discrete...
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| Format: | Others |
| Language: | en_US |
| Published: |
1995
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| Online Access: | http://ndltd.ncl.edu.tw/handle/30888868208864499827 |
| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 83 === This thesis is focused on the system-level design of the image
compression coder chip for the CCITT H.261 standard. An H.261
coder consists of several operation units such as motion
estimation, discrete cosine transform, quantization, and
variable length coding etc. This thesis places more emphasis
on how to make efficient and economical connections between
various units. The issues under consideration are system
operating frequency, system synchronization, general logic
vs. memory circuit, the number of external bus, and processing
fabrication technologies.
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