| Summary: | 碩士 === 國立交通大學 === 資訊工程研究所 === 83 === Superscalar processors exploit the concurrent use of multiple
functional units by issuing multiple instructions to these
functional units. However, they still suffer from two
impediments: branch hazards and data dependencies. The
penalties caused by them in the processor can be minimized by
rearranging the instruction sequence with a hardware or
software approach. And register renaming is a very effective
technique in providing the freedom for moving instructions
around in the original instruction sequence. Register renaming
mechanism removes the anti- and output dependencies between
instructions to allow more independent instructions to execute
in parallel in superscalar processing. In x86 processors, there
are fewer general-purpose registers than those in a typical
RISC processor, and reusing of the registers in a program is
expected to be more frequent. Therefore, renaming the registers
to uncover the instruction parallelism is needed. However, a
32-bit extended register can be further divided into 16- or
8-bit independent registers in these processors, which makes
renaming very difficult. In this thesis, we propose two
renaming hardware schemes in an x86 superscalar processor, and
evaluate them on an aggressive superscalar processor machine
model with reservation stations and a reorder buffer. The
first of the two renaming schemes is an intuitive design, whose
hardware cost may make it less desirable; and the second is to
aim at reducing the hardware cost, with possibly deteriorated
performance. Simulation results show that the second scheme can
reduce the hardware cost while retaining about 99 percent of
the performance from the register renaming by the first scheme.
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