Yield Analysis with Division of Sections and Redundancy Scheme for DARM

• Main Authors: Shih Dian Chan, 陳細鈿
• Other Authors: Lee-Ing Tong;Wei-I Lee
• Format: Others
• Language: zh-TW
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/70188316853130537127

碩士 === 國立交通大學 === 工業工程研究所 === 83 === With the increase in memory density, large chip size, small pattern size, and complicated cell structure, achieving high yield is hindered. Therefore, it is an important issue surrounding the IC industrial to maintain an effectively high yield. With an increasing yield of DRAM's, it is also an important factor that the design of circuits in wafer improves the manufacturing process and reduces defects. In general, the typical chip architecture of DRAM's is divided into various sections. The spare elements are prepared in each section. The section division and number of spare elements effectively impact yield and the cost of chips. Therefore, it is very important to establish a yield model which can accurately analyze section division and the number of spare elements. The yield model employed analyze section division and the number of spare elements based on negative bynomial yield model. This yield model is established by the architecture of 16 Mb DRAM's. The data of redundancy scheme is obtained by observing bitmap of 16 Mb DRAM's and employed to compute the unknown parameters of the negative bynomial yield model. It is proposed that the optimized section division and redundancy scheme of 16 Mb DRAM' s can reach the decided yield model.