A bit-level systolic array for matrix multiplication and its application to autoassociative memory

• Main Authors: Gui-Bin Hsieh, 謝貴彬
• Other Authors: Chi-Wu Mao, Chin-Hsing Chen
• Format: Others
• Language: en_US
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/06369411727618208389

碩士 === 國立成功大學 === 電機工程研究所 === 83 === In this thesis, a bit-level systolic array by two level pipelining method is proposed to implement the fast algorithm of matrix multiplication. After studting various current algorithms , in order to improve the efficiency and computation speed of every processor, firstly, we utilize the torus array of the standard multiplication algorithm in the word-level pipelining, then make a bit-level pipelining inside each processor. Because the number of processor is dependent on the dimension of the matrix and the number of bits of entry, we design two kinds of architectures for different conditions to reduce the complexity of the hardware. One is adapted to the "larger dimension" condition, the other is adapted to the "larger number of bits" condition. Finally, the above methods are applied in the field of neural network, and a bit-level systolic array for autoassociative memory is designed.